cystech electronics corp. spec. no. : c915s3 issued date : 2017.02.06 revised date : page no. : 1/9 MTA340N02S3 cystek product specification 20v n-channel enhancement mode mosfet MTA340N02S3 features ? simple drive requirement ? small package outline ? esd protected gate ? pb-free lead plating and halogen-free package symbol outline ordering information device package shipping MTA340N02S3-0-t1-g sot-323 (pb-free lead plating and halogen-free package) 3000 pcs / tape & reel MTA340N02S3 sot-323 g gate s source d drain g s d bv dss 20v i d @v gs =4.5v, t a =25 c 0.8a r dson @v gs =4.5v, i d =650ma 264m (typ) r dson @v gs =2.5v, i d =500ma 325m (typ) r dson @v gs =1.8v, i d =200ma 371m (typ) environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, t1 : 3000 pcs / tape & reel,7? reel product rank, zero for no rank products product name
cystech electronics corp. spec. no. : c915s3 issued date : 2017.02.06 revised date : page no. : 2/9 MTA340N02S3 cystek product specification absolute maximum ratings (ta=25 c) parameter symbol limits unit drain-source voltage v ds 20 gate-source voltage v gs 12 v continuous drain current @ t a =25 c, v gs =4.5v (note 3) 0.8 continuous drain current @ t a =70 c, v gs =4.5v (note 3) i d 0.64 pulsed drain current (notes 1, 2) i dm 3.2 a maximum power dissipation@ t a =25 (note 3) p d 0.34 w operating junction and storage temperature range tj ; tstg -55~+150 c thermal performance parameter symbol limit unit thermal resistance, junction-to-ambient, max (note3) r ja 367 thermal resistance, junction-to-case, max r jc 250 c/w note : 1. pulse width limited by maximum junction temperature. 2. pulse width 300 s, duty cycle 2%. 3. surface mounted on 1 in2 copper pad of fr-4 board; 270 c/w when mounted on minimum copper pad electrical characteristics (tj=25 c, unless otherwise noted) symbol min. typ. max. unit test conditions static bv dss 20 - - v gs =0v, i d =250 a v gs(th) 0.45 - 1.0 v v ds =v gs , i d =250 a i gss - - 10 v gs = 10v, v ds =0v - - 1 v ds =20v, v gs =0v i dss - - 25 a v ds =16v, v gs =0v(tj=70 c) - 264 350 v gs =4.5v, i d =650ma - 325 660 v gs =2.5v, i d =500ma *r ds(on) - 371 2000 m v gs =1.8v, i d =500ma *g fs - 2.4 - s v ds =5v, i d =1a dynamic ciss - 64 - coss - 17 - crss - 20 - pf v ds =10v, v gs =0v, f=1mhz t d(on) - 2.6 - t r - 16 - t d(off) - 29.8 - t f - 11 - ns v ds =10v, i d =0.5a, v gs =10v, r g =1 qg - 1.3 - qgs - 0.5 - qgd - 0.1 - nc v ds =15v, i d =0.5a, v gs =4.5v
cystech electronics corp. spec. no. : c915s3 issued date : 2017.02.06 revised date : page no. : 3/9 MTA340N02S3 cystek product specification source-drain diode *i s - - 0.8 *i sm - - 3.2 a *v sd - 0.8 1 v v gs =0v, i s =150ma trr - 4.9 - ns qrr - 1.0 - nc v gs =0v, i f =0.5a, di f /dt=100a/ s *pulse test : pulse width 300 s, duty cycle 2% recommended soldering footprint
cystech electronics corp. spec. no. : c915s3 issued date : 2017.02.06 revised date : page no. : 4/9 MTA340N02S3 cystek product specification typical characteristics typical output characteristics 0.0 0.5 1.0 1.5 2.0 2.5 3.0 01234 5 v ds , drain-source voltage(v) i d , drain current(a) 10v, 9v, 8v, 7v, 6v, 5v, 4v, 3v, v gs =1.5v 2 v brekdown voltage vs ambient temperature 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) bv dss , normalized drain-source breakdown voltage i d =250 a, v gs =0v static drain-source on-state resistance vs drain current 100 1000 0.01 0.1 1 10 i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =2.5v v gs =4.5v v gs =10v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 00.511.522.53 i dr , reverse drain current(a) v sd , source-drain voltage(v) static drain-source on-state resistance vs gate-source voltage 0 100 200 300 400 500 600 700 800 900 1000 024681 0 tj=25c v gs =0v tj=150c drain-source on-state resistance vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) r ds(on) , normalized static drain- source on-state resistance v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =650ma v gs =4.5v, i d =650ma r ds( on) @ tj=25c :264m
cystech electronics corp. spec. no. : c915s3 issued date : 2017.02.06 revised date : page no. : 5/9 MTA340N02S3 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 10 100 1000 02468 10 threshold voltage vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) v gs(th) , normalized threshold voltage v ds , drain-source voltage(v) capacitance---(pf) i d =1ma ciss crss i d =250 a c oss forward transfer admittance vs drain current 0.01 0.1 1 10 0.001 0.01 0.1 1 10 i d , drain current(a) g fs , forward transfer admittance(s) pulsed ta=25c v ds =5v v ds =10v gate charge characteristics 0 2 4 6 8 10 00.511.522.53 qg, total gate charge(nc) v gs , gate-source voltage(v) i d =0.5a v ds =15v maximum safe operating area 0.01 0.1 1 10 0.01 0.1 1 10 100 v ds , drain-source voltage(v) i d , drain current(a) dc 10ms 100ms 1ms 100 s t a =25c, tj=150c,v gs =4.5 v r ja =367c/w, single pulse 1s r ds( on) limited maximum drain current vs junctiontemperature 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 25 50 75 100 125 150 175 tj, junction temperature(c) i d , maximum drain current(a) t a =25c, v gs =4.5v, r ja =367c/w single pulse
cystech electronics corp. spec. no. : c915s3 issued date : 2017.02.06 revised date : page no. : 6/9 MTA340N02S3 cystek product specification typical characteristics(cont.) typical transfer characteristics 0.0 0.5 1.0 1.5 2.0 2.5 3.0 012345 v gs , gate-source voltage(v) i d , drain current(a) v ds =5v power derating curve 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0 50 100 150 200 t a , ambient temperature() p d , power dissipation(w) mounted on fr-4 board with 1 in 2 pad area transient thermal response curves 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 t 1 , square wave pulse duration(s) r(t), normalized transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r ja (t)=r(t)*r ja 2.duty factor, d=t 1 /t 2 3.t jm -t a =p dm *r ja (t) 4.r ja =367 c/w
cystech electronics corp. spec. no. : c915s3 issued date : 2017.02.06 revised date : page no. : 7/9 MTA340N02S3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c915s3 issued date : 2017.02.06 revised date : page no. : 8/9 MTA340N02S3 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note :1. all temperatures refer to topside of the package, measured on the package body surface. 2.for devices mounted on fr-4 pcb of 1.6mm or equivalent grade pcb. if other grade pcb is used, care should be taken to match the coeffi cients of thermal expansion betw een components and pcb. if they are not matched well, the solder joints may cr ack or the bodies of the parts may crack or shatter as the assembly cools.
cystech electronics corp. spec. no. : c915s3 issued date : 2017.02.06 revised date : page no. : 9/9 MTA340N02S3 cystek product specification sot-323 dimension marking: te n3 date code 3-lead sot-323 plastic surface mounted package cystek package code: s3 style: pin 1.gate 2.source 3.drain millimeters inches millimeters inches dim min. max. min. max. dim min. max. min. max. a 0.900 1.100 0.035 0.043 e1 2.150 2.450 0.085 0.096 a1 0.000 0.100 0.000 0.004 e 0.650 typ 0.026 typ a2 0.900 1.000 0.035 0.039 e1 1.200 1.400 0.047 0.055 b 0.200 0.400 0.008 0.016 l 0.525 ref 0.021 ref c 0.080 0.150 0.003 0.006 l1 0. 260 0.460 0.010 0.018 d 2.000 2.200 0.079 0.087 0 8 0 8 e 1.150 1.350 0.045 0.053 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing spec ification or packing method, please cont act your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitab le for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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